1. Field of the Invention
The present invention relates to an information processing system and a control method thereof, and more particularly to an information processing system including a semiconductor device with a self-refresh mode and a control method thereof. The present invention also relates to a control method of a controller, and more particularly to a controller that controls a semiconductor device with a self-refresh mode and a control method thereof.
2. Description of Related Art
An operation mode called a self-refresh mode is provided for the DRAM. The self-refresh mode is a kind of standby mode in which refresh of storage data included in storage cells is periodically performed inside of the DRAM in asynchronism with outside. A controller can stop issuance of many external signals such as an external clock signal and a command signal to be supplied to the semiconductor device, during a period when the semiconductor device has entered the self-refresh mode. During the period when the semiconductor device has entered the self-refresh mode, an input first-stage circuit such as a clock receiver included in the DRAM to receive a signal supplied from outside is inactivated and operations of circuit blocks such as the DLL circuit are also stopped. Accordingly, when the semiconductor device has entered the self-refresh mode, entire power consumption of the system becomes quite low. Furthermore, the refresh operation is periodically performed inside of the DRAM, so that the storage data are not lost.
On the other hand, the DRAM often has a function called ODT (On Die Termination). The ODT function enables a data terminal included in the DRAM to be used as a termination resistor. When the DRAM with the ODT function is used, signal quality of read data and write data can be enhanced without using an external termination resistor outside of the semiconductor device. For example, the ODT function is dynamically controlled by an impedance control signal issued from a controller.
However, because the impedance control signal is introduced inside of the DRAM in synchronism with an external clock signal, there is a problem that the impedance control signal cannot be used during a period when the semiconductor device has entered a self-refresh mode in which an input first-stage circuit such as a clock receiver is inactivated. Japanese Patent Application Laid-open No. 2001-332086 describes a DRAM that continuously receives an external clock signal even during a period when a semiconductor device has entered a self-refresh mode.
When having entered the self-refresh mode, the controller cannot use the ODT function. When data terminals of two semiconductor devices are connected with each other and one of the semiconductor devices is set to the self-refresh mode, data cannot be read from or write into the other semiconductor device. Therefore, the controller has no alternative but to enter a power-down mode in which the ODT function can be used; however, power consumption is higher in the power-down mode than in the self-refresh mode.
As to how the DRAM described in Japanese Patent Application Laid-open No. 2001-332086 handles an impedance control signal during a period when the semiconductor device has entered the self-refresh mode is unexplained. Furthermore, because a clock receiver is always activated in the DRAM described in Japanese Patent Application Laid-open No. 2001-332086, power consumption of the clock receiver cannot be reduced even when the semiconductor device enters the self-refresh mode.
This problem occurs not only in the DRAM but also in all semiconductor devices with the ODT function or the self-refresh mode. For example, there is the same problem also in a nonvolatile memory, a controller thereof, and a system, which are required to operate at high frequency. Further, there is the same problem also in a semiconductor device that in a part includes nonvolatile memory cells having a problem of cell data retention.